The invention relates to memory devices, and more particularly to a phase change memory (PCM) device and a method for fabricating the same.
Phase change memory devices are non-volatile, highly readable, highly programmable, and require a relatively lower driving voltage/current. Current trends in phase change memory development are to increase cell density and reduce current density thereof.
Phase change material in a phase change memory device has at least two solid phases, a crystalline state and an amorphous state. Transformation between these two phases can be achieved by changing the temperature of the phase change material. The phase change material exhibits different electrical characteristics depending on its state. For example, in its amorphous state the material exhibits a higher resistivity than in the crystalline state. Such phase change material may switch between numerous electrically detectable conditions of varying resistivities within a nanosecond time scale with the input of pico joules of energy. Since phase change material permits reversible phase transformation, memory bit status can be distinguished by determining the phase of phase change material in the memory bit.
FIG. 1 is a schematic diagram showing a cross sectional view of a conventional phase change memory cell structure. As shown in FIG. 1, the phase change memory cell structure includes a silicon substrate 10 with a bottom electrode 12 made of conductive material such as Al or W thereon. A dielectric layer 14 is formed over the bottom electrode 12 and a heating electrode 16 is formed in a portion of the dielectric layer 14. Moreover, a patterned phase change material layer 20 is stacked over the dielectric layer 14. The patterned phase change material layer 20 is formed within a dielectric layer 18 which is formed over the dielectric layer 14 and a bottom surface of the phase change material layer 20 partially contacts the heating electrode 16. A dielectric layer 24 is formed over the dielectric layer 18 and a top electrode 22 is formed over and in the dielectric layer 24. The top electrode 22 partially covers the dielectric layer 24 and portions thereof protrude downward through the dielectric layer 24, thereby contacting the phase change material layer 20 thereunder.
In a write mode, a large current is generated by the heating electrode 16 and flows therethrough, thus heating up an interface between the phase change material layer pattern 20 and the heating electrode 16 and thereby transforming a portion (not shown) of the phase change material layer 20 into either the amorphous state or the crystalline state depending on the length of time and amount of current that flows through the heating electrode 16.
One problem is found with conventional phase change transistors is the relatively large amount of reset current required to successfully change the state of the phase change material during a write operation. One solution to reduce reset current required and to successfully turn on the phase change reaction is to reduce the contact surface between the heating electrode 16 and the phase change material layer 20, such as through reducing a diameter D0 of the heating electrode 16, thereby maintaining or increasing a current density at the interface.
Reduction of the diameter D0 of the heating electrode 16, however, is limited by current photolithography process ability, thereby limiting size reduction of the heating electrode 16 and ability to decrease current density.